1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
In manufacturing SRAMs, first, mask patterns are made based on patterns that are designed by the designers. Resists are exposed using the mask patterns to make resist patterns. Using the resist patterns, conduction layers and the like formed on a semiconductor substrate are selectively etched to form patterns for a memory circuit on the semiconductor substrate.
In the manufacturing of the SRAM described above, when a mask pattern is completely identical with a designed pattern, a resist pattern is not formed faithfully with respect to the designed pattern due to light proximity effect. In particular, narrow end sections of wirings have small focusing margins in the exposure and they cause rounded or receded end sections in the resist pattern. Also, when contact holes are located in end sections of wirings, problems occur. For example, an enclosure (an extra coverage for the wiring above or below the contact hole) of the contact deteriorates, which results in an increased resistance, opens the connection, and causes other problems. For this reason, mask patterns, with the light proximity effect being corrected with respect to the designed patterns, are used. However, patterns with finely corrected measurements are required to correct the light proximity effect, and therefore the cost for the masks increases. Also, steps for confirming the corrected patterns are required, which result in a longer period for developing SRAMs and an increase in development costs.
Also, hand-carry type equipment on which SRAMs are mounted need to be reduced in size, and therefore the memory size of the SRAMs must be reduced.
It is an object of the present invention to provide a highly reliable semiconductor memory device that enhances manufacturing and reproducibility of wiring patterns.
It is another object of the present invention to provide a semiconductor memory device that can alleviate the correction of the light proximity effect.
It is a further object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device has a memory cell that includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor and a second transfer transistor. The semiconductor device includes a first drainxe2x80x94drain connection layer and a second drainxe2x80x94drain connection layer. The first drainxe2x80x94drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drainxe2x80x94drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. Each of the first drainxe2x80x94drain connection layer and the second drainxe2x80x94drain connection layer includes a first contact end section, a second contact end section, a linear section and an extension section. The first contact end section of the first drainxe2x80x94drain connection layer is a portion that connects to the drain region of the first driver transistor. The second contact end section of the first drainxe2x80x94drain connection layer is a portion that connects to the drain region of the first load transistor. The linear section of the first drainxe2x80x94drain connection layer is a portion that linearly extends from the first contact end section of the first drainxe2x80x94drain connection layer and reaches the second contact end section of the first drainxe2x80x94drain connection layer. The extension section of the first drainxe2x80x94drain connection layer is a portion that extends from the second contact end section of the first drainxe2x80x94drain connection layer in a direction toward a location where the second drainxe2x80x94drain connection layer is located. The first contact end section of the second drainxe2x80x94drain connection layer is a portion that connects to the drain region of the second driver transistor. The second contact end section of the second drainxe2x80x94drain connection layer is a portion that connects to the drain region of the second load transistor. The linear section of the second drainxe2x80x94drain connection layer is a portion that linearly extends from the first contact end section of the second drainxe2x80x94drain connection layer and reaches the second contact end section of the second drainxe2x80x94drain connection layer. The extension section of the second drainxe2x80x94drain connection layer is a portion that extends from the second contact end section of the second drainxe2x80x94drain connection layer in a direction toward a location where the first drainxe2x80x94drain connection layer is located.
In accordance with the present invention, the extension section prevents the second contact end sections of the drainxe2x80x94drain connection layer from being rounded or receded. Therefore, the enclosure of a contact hole disposed at the second contact end section is prevented from deterioration. Accordingly, in accordance with the present invention, process margins for a semiconductor memory device and its reliability can be enhanced.
Also, in accordance with the present invention, the extension sections correct the light proximity effect. Therefore, devices, such as shelves or the like to correct the light proximity effect, do not need to be added to the second contact end section of the second drainxe2x80x94drain connection layer. Accordingly, the correction of the light proximity effect can be alleviated, and the cost for semiconductor memory devices can be accordingly reduced.
In accordance with the present invention, another conduction layer is not located between the extension section of the first drainxe2x80x94drain connection layer and the extension section of the second drainxe2x80x94drain connection layer. In accordance with the present invention, since other conduction layers are not located in the region described above, the extension section can be formed without enlarging the area of the memory cell.
In accordance with the present invention, a distance between the first contact end section of the first drainxe2x80x94drain connection layer and the first contact end section of the second drainxe2x80x94drain connection layer is longer than a distance between the extension section of the first drainxe2x80x94drain connection layer and the extension section of the second drainxe2x80x94drain connection layer. In accordance with the present invention, the distance between the first contact end section of the first drainxe2x80x94drain connection layer and the first contact end section of the second drainxe2x80x94drain connection layer is relatively long, such that another conduction layer can be disposed in a region between them.
The present invention includes a first gate electrode layer, a second gate electrode layer, a first drain-gate connection layer and a second drain-gate connection layer. The gate electrode layers, the drainxe2x80x94drain connection layers and the drain-gate connection layers are located in different layers. In plan view, the first gate electrode layer and the second gate electrode layer are located between the first drainxe2x80x94drain connection layer and the second drainxe2x80x94drain connection layer. The first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor. The second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor. The first drain-gate connection layer connects the first drainxe2x80x94drain connection layer. The second gate electrode layer, and the second drain-gate connection layer connects the second drainxe2x80x94drain connection layer and the first gate electrode layer.
The present invention is equipped with gate electrode layers that become gates of inverters, drainxe2x80x94drain connection layers that connect drains of the inverters, and drain-gate connection layers that connect gates of one of the inverters and drains of the other of the inverters. A semiconductor memory device in accordance with the present invention uses three layers (gate electrode layers, drainxe2x80x94drain connection layers, and drain-gate connection layers) to form flip-flops. Accordingly, patterns in each layer can be simplified (for example, into linear patterns) compared to the case in which flip-flops are formed using two layers. In this manner, in the semiconductor memory device in accordance with the present invention, the patterns in each layer can be simplified. As a result, a miniaturized semiconductor memory device with its memory cell size being 4.5 xcexcm2 or smaller, for example, can be manufactured.
Also, in accordance with the present invention, in plan view, the first and second gate electrode layers are located between the first drainxe2x80x94drain connection layer and the second drainxe2x80x94drain connection layer. As a result, the source contact layer of the driver transistors can be disposed in the central area of the memory cell. Furthermore, wirings that are located in the same layer as the drainxe2x80x94drain connection layers and to be connected to the source contact layers can be disposed in the center of the memory cell. Accordingly, the degree of freedom in forming the first and second drain-gate connection layers increases. This is also advantageous with regard to reducing the memory cell size.
Also, in accordance with the present invention, the source region of the two driver transistors within a memory cell can be disposed in the central area of the memory cell, and the source contact layer can be commonly used within the cell. As a result, increases in the source potential, that may be caused by the source contact parasitic resistance, can be made uniform without regard to read data, and therefore a highly stable semiconductor memory device can be realized.
In accordance with the present invention, the first drainxe2x80x94drain connection layer is connected to the first drain-gate connection layer at the second contact end section of the first drainxe2x80x94drain connection layer, and the second drainxe2x80x94drain connection layer is connected to the second drain-gate connection layer at the first contact end section of the second drainxe2x80x94drain connection layer. In accordance with the present invention, the positions of contacts that connect the drainxe2x80x94drain connection layers to the drain-gate connection layers can be separated from the cell center and from one another diagonally across the cell center. Accordingly, the drain-gate connection layer can be formed in a simple pattern in an L-letter shape. As a result, while the cell area is reduced, the processing rule for making the drain-gate connection layers can be lightened.
In accordance with the present invention, the first contact end section of the second drainxe2x80x94drain connection layer is wider than the first contact end section of the first drainxe2x80x94drain connection layer, and the extension section of the second drainxe2x80x94drain connection layer is shorter than the extension section of the first drainxe2x80x94drain connection layer. In accordance with the present embodiment, the enclosure of a contact that connects the drainxe2x80x94drain connection layer to the drain-gate connection layer can be expanded, and a greater margin for positioning can be obtained.
In accordance with the present invention, the first drainxe2x80x94drain connection layer is connected to the first drain-gate connection layer at the first contact end section of the first drainxe2x80x94drain connection layer, and the second drainxe2x80x94drain connection layer is connected to the second drain-gate connection layer at the second contact end section of the second drainxe2x80x94drain connection layer. In accordance with the present invention, the positions of contacts that connect the drainxe2x80x94drain connection layers to the drain-gate connection layers can be separated from one another diagonally across and from the cell center. Accordingly, the drain-gate connection layer can be provided with a simple pattern in an L-letter shape. As a result, the processing rule for making the drain-gate connection layers can be eased without reducing the cell area.
In accordance with the present invention, the first contact end section of the first drainxe2x80x94drain connection layer is wider than the first contact end section of the second drainxe2x80x94drain connection layer, and the extension section of the first drainxe2x80x94drain connection layer is shorter than the extension section of the second drainxe2x80x94drain connection layer. In accordance with the present embodiment, the enclosure of a contact that connects the drainxe2x80x94drain connection layer to the drain-gate connection layer can be expanded, and a greater margin for positioning can be obtained.
In accordance with the present invention, each of the first gate electrode layer and the second gate electrode layer has a linear pattern. The first gate electrode layer, the second gate electrode layer, the linear section of the first drainxe2x80x94drain connection layer, and the linear section of the second drainxe2x80x94drain connection layer are disposed in parallel with one another. In accordance with the present embodiment, the patterns are simple, and therefore a semiconductor memory device with a very small memory cell size can be realized.
In accordance with the present invention, the first and second driver transistors are n-type, the first and second load transistors are p-type, and the first and second transfer transistors are n-type. The present invention further includes first, second, third and fourth conduction layers. The first gate electrode layer, the second gate electrode layer and an auxiliary word line are located in the first conduction layer. The first drainxe2x80x94drain connection layer, the second drainxe2x80x94drain connection layer, a power supply line, a first contact pad layer, a second contact pad layer and a third contact pad layer are located in the second conduction layer. The first drain-gate connection layer, the second drain-gate connection layer, a main word line, a fourth contact pad layer, a fifth contact pad layer and a sixth contact pad layer are located in the third conduction layer. A first bit line, a second bit line and a grounding line are located in the fourth conduction layer. The auxiliary word line extends in a first direction. The power supply line connects to source regions of the load transistors. The first contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The second contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The third contact pad layer is used to connect source regions of the driver transistors and the grounding line. The main word line extends in the first direction. The fourth contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The fifth contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The sixth contact pad layer is used to connect source regions of the driver transistors and the grounding line. The first and second bit lines extend in a second direction that is perpendicular to the first direction.
In accordance with the present invention, a variety of characteristics required for semiconductor memory devices (for example, reduced size, reliability, stability and speed) can be enhanced in a well-balanced manner.